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Experienced, self-motivated technical professional with nineteen years experience utilizing all levels of physical design, which draw on problem-solving strengths. Strengths include floor planning, layout and verification of high speed RF circuits.
Top level floor planning, layout and full chip verification of 10Gb/s (OC192) transceivers, designed to address future systems of 40Gb/s (OC-768), using TSMC .13um technology. Circuits include: VCO’s VCOBUFFER’S, Demuxes, Voltage Regulator’s, DAC’s, Loopfilter’s, Ring Oscillators, Bias Blocks, ESD Structures, standard cell libraries and other various high speed digital blocks.
Development and implementation of standard design kit elements. Elements include: interdigitated metal capacitors, inductors, varactors and transmission lines. Mentor Graphics rule deck development using Skill code.
Mentor and instruct junior layout engineers both in New Jersey and Germany on physical practices.
Proficient Cadence and Mentor Graphics tool experience. Familiar with IBM, Lucent and TSMC foundry procedures; .5, .35, .18, .15, .13, .09um (Lucent/TSMC), 7SF, 7HP, 6HP, .18, .13um RF CMOS and LVOD.
Close attention to matching, electron migration, symmetry, power bussing, balancing of critical signals and IR drop.
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CADMASTER1
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Home » Education & Tutoring » Engineering » Electrical Engineering
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